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Total experience of 8 YEARS as FPGA IP Design engineer. 4 Years of experience as FPGA IP DESIGN ENGINNER AT INTEL/Altera. 1 Year 6 months of experienc... View More
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- VSD- Static Timing Analysis - I and VSD- Static Timing Analysis - II on Udemy. The certificate earned in May 2018. System Verilog Beginner: Write Your First Design and Test Bench Module on Udemy. The certificate earned in June 2018. System Verilog Function Coverage Language/Methodology/apps on Udemy. The certificate earned on July 2018. Attended the workshop on ARDUINO BOT conducted by Robosoft systems at the IIT-Bombay Attended the workshop on LabVIEW Programming conducted by Measurement's & sensor Division at VIT University, Vellore.
Skilled Embedded Software Developer with 12 years of experience in programming, software design, analysis, testing, and debugging. Expertise in develo... View More