clock tree synthesis Search Results

Working as Senior Lead Design Engineer at NXP Semiconductor with 10 years of experience in Physical Design, Physical Verification and IR analysis. Wor... View More

STA engineer with experience in block-level timing closure, constraints development and cross-block timing analysis. Skilled in managing setup/hold cr... View More

A Master's graduate in Integrated Circuits Design with 3+ years of experience, seeking an IC design role to contribute and grow in the semiconductor i... View More

Digital Design Engineer with over 13 years of expertise in RTL design, verification, and backend implementation. Specializes in high-speed, low-power ... View More

Experienced Physical Design Engineer with a strong background in implementing physical design strategies and conducting static timing analysis. Profic... View More

Physical Design Engineer with 3+ years of experience in advanced nodes (5nm/6nm/7nm), owning end-to-end block implementation from synthesis to sign-of... View More

Having solid experience in physical design engineering. Skilled in IC design, layout optimization, and timing analysis. Strong focus on team collabora... View More

Skilled Software Engineer with extensive experience in Ethernet and Power modules, delivering critical communication and power solutions. Proficient i... View More

Professional scientist with significant experience in laboratory chemical analysis and research. Skilled in various analytical techniques, including c... View More

Experienced VLSI Engineer with 2.8 years of expertise in Synthesis, Logic Equivalence Check (LEC), and Static Timing Analysis (STA). Proficient in u... View More