Rajiv Hasija

Roles and Responsibilities : Testbench Development, Review,Project Ownership and Execution

Project Work :

RISC-V core DV Project (Team size: 3): •

Testbench Development :

Developed the FE SS DV (front end) with multiple BFMs, scoreboards, golden reference model

Developed the complete Core DV environment using open source tools (Spike, DIFFTEST), VIPs, to verify core in lock step verification •

Enhanced and modified Google RISC-V DV to add DUT specific features to generate comprehensive stimulus for branch prediction and other front end IPs

Developed 3 IP DV environment (ICache, Fetch unit, Branch prediction and Fetch target queue IP

RISC-V SoC and RISC-V core DV Project (Team size 2) : •

Developed Complete UVM based RISC-V SoC DV environment from scratch with scoreboard, checkers for BUS DV, Cache coherency, peripherals checkers, RAL etc.

Developed comprehensive all features inclusive VIP for TL-C protocol (slave, master), L2, L1 cache models (FSMs, checkers, memory, directory, debugging infra, performance monitors) •

Team Management, Reporting and Status tracking •

Automotive SoC :

Project Execution Ownership : Multiple SS DV ownership BUS DV(Interconnect DV), CMU, Power, functional safety for an NPU SoC

Achievements •

Level up - Spearheaded initiative to enhance team techinical capabilities and productivity, by giving techinical seminar s, automation , process optimization.

• Roles and Responsibilities :
• Team Management/Stakeholders Management :
• Resource allocation and planning , Performance Appraisal, Team Motivation/Engagement, Managing Hiring/Attrition.
• Building/Strengthening Customer relationship ,Customer Satisfaction, Expanding scope and ownership of India team.
• Project Management/Execution :
• Project : Project tracking , Task allocation, Risk Mitigation , Reviews Process/Efficiency improvements, Training , Ramp up and Support
• Project Execution :
• Achievements
• Standardized the DV project tracking process by consolidating DV MS checklists , Key Indicators, Dashboards, Reporting , Deliverables definition, Cross functional alignment.
• Project Work :
• IP SS Ownership : Ownership of complete IO SS for RTL , DV , PD for all projects. Driving all 3 functions for timely completion of all MS in compliance with PLC requirements - Ongoing
• IPU SoC DV Ownership : Driving the Global DV activities across 3 Geos , ensuring all process , methodology , cross functional deliveries are tracked and delivered on time - Project on hold
• IP/SS DV Ownership/Support : Ownership and Support for IP/S DV across projects, Peri Ctrl, DDR SS.

• Roles and Responsibilities :
• Team Management :
• Resource allocation and planning , Performance Appraisal, Team Motivation/Engagement, Managing Hiring/Attrition, Vendor management, Leadership Development.
• Stakeholders Management :
• Building/Strengthening Customer relationship ,Customer Satisfaction, Expanding scope and ownership of India team, Ensuring Security/Policy compliance, Updating/Assisting Top Management.
• Project Management/Execution :
• Reviews : Testplan , HDD/SOR , Testbench architecture
• Project : Project tracking , Task allocation, Risk Mitigation , Process/Efficiency improvements, Training , Ramp up and Support
• Project Execution :
• Achievements
• Started and Built SoC/IP team from 8 members to 45+ member team in 3 years
• Participated in DV for all 5G Mobile SoC(15+) including S21/Note 20.
• Complete ownership of multiple BLKs/IPs at SSIR for all SoCs.
• Received Inspiring Leadership Award from Customer VP.
• Highest ever team satisfaction survey(SCI Survey), with 0 attrition in 2020.
• Project Work :
• DV ownership for SoC Subsystem for all Mobile SoC projects - Completed Execution of 9 Mobile SoCs in 2020.
• DV Ownership of Multiple IPs in SSIR , including Packet Processor , XDMA , I3C , Turbo Decoder, SymbProc NR, Compression, Logger etc.
• Built emulation team for UVMA testbench and porting of long sims. Pre-Silicon Software bringup
• Multiple initiative like HLS , Technical papers, patent(1)
• Tracking , Reviewing testplan , debugging support, analyzing RTL Defect.

• Roles And Responsibilities : Testbench Architecture, Development, Project execution and Team Development.
• GDDR6/LPDDR5 BM development and Verification :
• Lead a team of 6 team members to develop the commercial grade BM for GDDR6/LPDDR5 and associated verification environment and its execution.
• Made block Verification Strategy, contributed towards Testplan, architected the testbench
• Directed the team to the execution of the testplan, meeting coverage targets.
• Task Allocation, Tracking the progress of the task assigned.
• Achievement : Given the President Appreciation Award for this project for delivering to Korea and supporting external client.
• RFX- SAS Host Controller Verification :
• Lead a team of eight team members to develop the complete verification environment and its execution.
• Made IP/Subsystem level Verification Strategy, contributed towards Testplan, Defined testbench architecture,Implemented scoreboard, many checkers, owned the subsystem level random test scenarios.
• Directed the team for testplan execution, coverage closure.
• Achievement : Awarded President Award for this project. Zero Silicon Bug. Received project of the year award.

• EPIC- SCSIe Host Controller Verification – Industry First NVMe based enterprise SSDs
• Lead a team of four people to develop the complete verification environment and its execution Testplan.
• Implemented scoreboard, a few checkers and DUT algorithms
• Achievement : Given the Knight Award for this project.
• MDX/MEX/VLX/MFX- Flash Subsystem Verification :
• Lead a team of four people to develop the complete verification environment and its execution.
• Made block Testplan , Testbench development , coverage models
• Understood the working of uCode(Assembly) and its modification
• Development of C-Model for LDPC IP.
• Created the script for the UVM - RAL(Register Model ) model generation from XLS file, which is being used across all projects now
• Created the infrastructure(IOTA Script-Python) for compiling, running testcases , regression , log files etc with various options which is being used across many projects

• DDR3 Memory Controller and DDR3 Phy Verification in Memory Subsystem
• Made block Verification Strategy and Verification Environment component enhancements. SV based OVM methodology.
• TB Components(Sequences SCBD, Coverage, Assertions etc) development and execution of testplan
• Debugged and Enhanced the various Training/Leveling algorithms
• Helped FW and validation team in bringing up the DDR3 on board. Active support for many customer related issue.

• AHB Complex Verification
• UFC (Universal Flash Controller NAND(ONFI)/NOR/SRAM ) Verification, SDHC and TDM Verification
• Development Including Scoreboard, Interfaces and Assertions, Denali Drivers/Monitors Integration
• Integration and score boarding for AXI/AHB Master and slave BFM
• Automation using perl and configuration interface using C++ DPI interface of SV

• PCM-Packet Processor Block : Made a complete Verification Environment independently using Synopsys VMM Methodology.
• Made 3 Reusable VIP(verification IP's) -Included Generators,Drivers,Monitors,Scoreboards,Interfaces,Checkers,Configurations
• Testplan execution and DV completion
• CTB(Control Subsystem Block)/EPP(Egress Packet Processor) : Developed VIP for PBI, VCI2, I2C interface block in SV/C++ based testbench and verified the DUT

• RTL Design of Output Interface of the VOUT/BITOUT Block in VHDL.
• Developed Test Environment, wrote testbenches and scripts for the verification of the VIN/BITIN Block
• Developed the complete C-Model and Test Environment for the verification of the Davis Display Block IC and ran regression to complete the verification