SEAN GALLOWAY

PROFILE SUMMARY Highly ambitious and experienced Senior Design Engineer skilled in RTL design for timing, Intel process technology, design rules and layout, and verification flows. Proficient in identifying, qualifying, documenting, and releasing components that meet regulatory standards for applicable electronic and electromechanical component commodities. Adept at executing component quality development, maintenance, failure analysis, and resolution activities. Excellent communicator and team leader who can manage multiple projects with competing deadlines. Solutions-oriented engineering professional with a strong understanding of product development process. Brings excellent interpersonal and communication skills to work effectively with colleagues, management and vendors. Proactive in identifying areas of improvement and taking steps to drive successful completion of projects.

• Before wavedrom became ubiquitous, created a Microsoft Excel spreadsheet flow that generates Visio waveforms. It is still widely used at Intel.
• Created a unified database that contained all of the Architectural and Design requirements for the config registers in an SoC. this unified database created the documentation and config RTL. this resulted in very few documentation and RTL bugs in configuration.
• Achieved doubling of the Front-Side Bus frequency by introducing changes to the board layout and many surgical changes to the data and control path.
• Micro-Architect on LPDDR4 PHY; ramped junior members on the architecture and collaborated with the Bios team.
• Micro-Architect for DFI Protocol Layer; designed AHB Sub-system and SPID-based PHY interface, a Minute-IA, and a complete North Bridge with a memory controller.
• Micro-Architect for Far Memory Interface; created a generic power management FSM for PHY.
• Lead Designer for LPDDR3 memory controller; collaborated with Emulation and Hard IP teams for support.
• Designer integrating the Power-VR graphics controller into multiple SoCs.

Patents:

• Prioritized address decoder, US-7610611-B2
• Method to integrate ARM ecosystem IPs into PCI-based interconnect, US-9164938-B2

My goal is to start folks off learning basic Python, System Verilog and the UVM methodology and slowly progress to designing their own RiscVI32 microprocessor, IO Sub-system, AMBA fabric, and possibly some Tensor Processing Units for inference experiments with the intent of loading this onto an appropriate FPGA. All the code in the repo is considered to be a jumping-off point. I expect and encourage others to make the code their own, like make personal async fifo's and possibly do it better than mine. All free tools are used in this project but also prepare folks to work in the industry.